View SSM2804_5345646.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

audio subsystem with class-d speaker and capless headphone driver SSM2804 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 3 single-ended stereo audio inputs with optional differential mode stereo, 1.4 w, filterless class-d amplifiers with - modulation integrated receiver path bypass switch configurable, high performance capless headphone output with true ground class-g technology optional hardware-based headphone level limiter i 2 c control interface volume control flexible input/output mixing output mode control emi emissions control automatic level control (alc) adjustable headphone level limiter low shutdown current short-circuit and thermal protection pop-and-click suppression available in a 30-ball, 2.5 mm 3.0 mm wlcsp applications mobile phones portable multimedia devices general description the SSM2804 is an audio subsystem designed specifically for mobile phones and portable multimedia devices. this highly flexible subsystem includes three input channels that can be configured as single-ended stereo or monaural differential for multimedia audio sources. each set of inputs is independently adjustable with the 2-wire i 2 c interface and features an adjustable gain over a 30 db range in steps of 1 db. each set of input channels also offers the choice of variable input impedance pga mode or fixed input impedance boost mode. the input signals are then mixed and routed to the desired set of outputs. this configuration is set using the 2-wire i 2 c control interface. the SSM2804 includes three selectable output modes. the first output mode is a stereo class-d speaker driver capable of delivering 2 1.4 w of continuous power to an 8 bridge-tied load (btl) with 1% thd + n when using a 5 v supply. this class-d amplifier incorporates three-level - output modulation designed to increase battery life and improve emi performance. the class-d amplifier offers an i 2 c-adjustable volume control with a gain range from +12 db to ?63 db in 31 steps. the second output mode is a pair of high performance head- phone drivers capable of delivering 20 mw per channel into stereo 32 single-ended loads with 1% thd + n. the stereo headphone drivers use a highly efficient, true ground centered class-g architecture. the headphone outputs incorporate i 2 c-adjustable volume control with a gain range from 0 db to ?75 db in 32 steps. the third output mode is an integrated receiver path bypass switch for passing voice signals from the audio baseband. the SSM2804 is specified over the industrial temperature range of ?40 c to +85 c. it has built-in thermal shutdown and output short-circuit protection. the SSM2804 is available in a 30-ball, 2.5 mm 3.0 mm wafer level chip scale package (wlcsp).
SSM2804 rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? functional block diagram .............................................................. 3 ? specifications ..................................................................................... 4 ? i 2 c timing characteristics .......................................................... 6 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? typical performance characteristics ............................................. 9 ? theory of operation ...................................................................... 13 ? pop-and-click suppression ....................................................... 13 ? output modulation description .............................................. 13 ? hardware-based headphone limiter ...................................... 14 ? activating or deactivating the emission limiting circuitry ... 14 ? automatic level control (alc) ............................................... 14 ? typical application circuits .......................................................... 17 ? i 2 c software control interface...................................................... 19 ? register map .................................................................................... 20 ? register map details ...................................................................... 21 ? input channel mode control, address 0x00 ......................... 21 ? channel a line input volume, address 0x01 ........................ 22 ? channel b line input volume, address 0x02 ........................ 23 ? channel c line input volume, address 0x03 ........................ 24 ? class-d left loudspeaker output volume, address 0x04 ... 25 ? class-d right loudspeaker output volume, address 0x05 ... 26 ? left headphone output volume, address 0x06 .................... 27 ? right headphone output volume, address 0x07 ................. 28 ? headphone input mixer control, address 0x08.................... 29 ? class-d input mixer control, address 0x09 .......................... 29 ? alc control 1, address 0x0a .................................................. 30 ? alc control 2, address 0x0b .................................................. 31 ? alc control 3, address 0x0c .................................................. 32 ? power-down control, address 0x0d ...................................... 32 ? additional control, address 0x0e ........................................... 34 ? chip status register, address 0x0f.......................................... 35 ? software reset register, address 0x10 .................................... 35 ? outline dimensions ....................................................................... 36 ? ordering guide .......................................................................... 36 ? revision history 7/11revision 0: initial version
SSM2804 rev. 0 | page 3 of 36 functional block diagram ep? ep+ lspk+ hpl lspk? rspk+ rspk? hpr 09960-001 boost = 0db to +20db pga = ?12db to +18db +12db to ?63db 31 steps class-d class-g 0db to ?75db 32 steps ina2 rcv? rcv+ ina1 boost = 0db to +20db pga = ?12db to +18db inb2 inb1 mix/mux boost = 0db to +20db pga = ?12db to +18db inc2 inc1 sd bias i 2 c class-g supply bias agnd pvdd a v dd SSM2804 cf1 cf2 cpvdd pgnd scl sda cpvss figure 1.
SSM2804 rev. 0 | page 4 of 36 specifications t a = 25c, avdd = 3.3 v, pvdd = 3.6 v, gain = 0 db, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments power supply analog voltage supply (avdd) 2.5 3.3 3.6 v speaker voltage supply (pvdd) 2.7 3.6 5.5 v total quiescent current (i dd ) 3.5 ma hp mode only 6.0 ma stereo class-d mode only 9.8 ma hp and class-d modes 400 a receiver path mode power-down current (i sd ) 1 a sd pin low input characteristics turn-on time 10 ms sd rising edge from agnd to avdd pga mode operation input impedance 38 54 k minimum gain setting 4.5 6.5 k maximum gain setting gain range ?12 +18 db inax , inbx, incx inputs, 31 steps boost mode operation input impedance 20 k gain range 0 20 db inax, inbx, incx inputs, 3 steps class-d amplifier output offset voltage (v os ) 2.3 mv output muted 12 mv output unmuted output power (p out ) f = 1 khz, mono operation 310 mw pvdd = 2.7 v, r l = 8 + 33 h, thd + n = 1% 700 mw pvdd = 3.6 v, r l = 8 + 33 h, thd + n = 1% 1.0 w pvdd = 4.2 v, r l = 8 + 33 h, thd + n = 1% 1.4 w pvdd = 5.0 v, r l = 8 + 33 h, thd + n = 1% 700 mw pvdd = 2.7 v, r l = 4 + 15 h, thd + n = 1% 1.5 w pvdd = 3.6 v, r l = 4 + 15 h, thd + n = 1% 2.0 w pvdd = 4.2 v, r l = 4 + 15 h, thd + n = 1% 2.9 w pvdd = 5.0 v, r l = 4 + 15 h, thd + n = 1% 400 mw pvdd = 2.7 v, r l = 8 + 33 h, thd + n = 10% 860 mw pvdd = 3.6 v, r l = 8 + 33 h, thd + n = 10% 1.2 w pvdd = 4.2 v, r l = 8 + 33 h, thd + n = 10% 1.7 w pvdd = 5.0 v, r l = 8 + 33 h, thd + n = 10% 900 mw pvdd = 2.7 v, r l = 4 + 15 h, thd + n = 10% 1.8 w pvdd = 3.6 v, r l = 4 + 15 h, thd + n = 10% 2.5 w pvdd = 4.2 v, r l = 4 + 15 h, thd + n = 10% 3.6 w pvdd = 5.0 v, r l = 4 + 15 h, thd + n = 10% total harmonic distortion plus noise (thd + n) 0.01 % r l = 8 + 33 h, p out = 250 mw output noise (v n ) 40 v 20 hz to 20 khz, a-weighted signal-to-noise ratio (snr) 94 db 2.0 v rms output, a-weighted, pvdd = 5 v power supply rejection ratio (psrr) 80 db 217 hz, 200 mv p-p ripple 80 db 1 khz, 200 mv p-p ripple common-mode rejection ratio (cmrr) 55 db differential input mode, 1 khz, 10 mv rms efficiency 89 % p out = 700 mw minimum load resistance (r load ) 4 average switching frequency (f sw ) 400 khz volume control gain range ?63 +12 db
SSM2804 rev. 0 | page 5 of 36 parameter min typ max unit test conditions/comments headphone output output offset voltage (v os ) 2 mv headphone only 8 mv inax, inbx, incx inputs output power (p out ) 20 mw r l = 32 , thd + n = 1% 40 mw r l = 16 , thd + n = 1%, 1 f charge pump capacitor total harmonic distortion plus noise (thd + n) 0.012 % r l = 32 , p out = 15 mw 0.02 % r l = 16 , p out = 10 mw output noise (v n ) 16 v 20 hz to 20 khz, a-weighted signal-to-noise ratio (snr) 96 db 800 mv rms output, a-weighted power supply rejection ratio (psrr) 95 db 217 hz, 200 mv p-p ripple 85 db 1 khz, 200 mv p-p ripple crosstalk 90 db 1 khz, p out = 12 mw minimum load resistance (r load ) 16 maximum capacitive load (c load ) 500 pf gain range ?75 0 db esd protection 8 kv receiver path (bypass switch) path impedance (r on ), receiver inputs to speaker outputs 1.5 rcv+ to ep+ and rcv? to ep? signal path thd + n 0.1 % p out = 70 mw, r l = 32 or p out = 17.5 mw, r l = 8 output noise 10 v 20 hz to 20 khz, a-weighted off channel isolation 90 db 217 hz, 200 mv p-p ripple input common mode pvdd/2 v table 2. digital logic levels (cmos levels) parameter min typ max unit input low level (v il ) 0.35 v input high level (v ih ) 1.35 v output low level (v ol ) 0.1 avdd v output high level (v oh ) 0.9 avdd v
SSM2804 rev. 0 | page 6 of 36 i 2 c timing characteristics table 3. parameter limit unit description t min t max t scs 600 ns start condition setup time t sch 600 ns start condition hold time t ph 600 ns scl pulse width high t pl 1.3 s scl pulse width low f scl 0 526 khz scl frequency t ds 100 ns data setup time t dh 900 ns data hold time t rt 300 ns sda and scl rise time t ft 300 ns sda and scl fall time t hcs 600 ns stop condition setup time timing diagram 09960-002 scl sda t rt t sch t pl t ds t ph t dh t ft t scs t hcs figure 2. i 2 c timing
SSM2804 rev. 0 | page 7 of 36 absolute maximum ratings t a = 25c, unless otherwise noted. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. parameter rating analog supply voltage (avdd) ?0.3 v to +3.6 v speaker supply voltage (pvdd) ?0.3 v to +3.6 v input voltage v dd sd , scl, sda, rcv+, rcv? ?0.3 v to +6.0 v ina1, ina2, inb1, inb2, inc1, inc2 ?0.3 v to avdd + 0.3 v esd (hbm) on headphone output 8 kv storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +165c lead temperature (soldering, 60 sec) 300c table 5. thermal resistance package type pcb ja jb unit 30-ball, 2.5 mm 3.0 mm wlcsp 1s0p 162 39 c/w 2s0p 76 21 c/w esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SSM2804 rev. 0 | page 8 of 36 pin configuration and fu nction descriptions 09960-003 top view (ball side down) not to scale 1 a b c d e 234 ball a1 corner 56 lspk+ pvdd rspk+ ep+ rcv+ ina1 lspk? pgnd rspk? ep? rcv? ina2 cf2 cpvss scl sda inb2 inb1 agnd cpvdd hpr sd inc2 inc1 cf1 avdd hpl agnd avdd bias figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic description a1 lspk+ class-d loudspeaker output left + b1 lspk? class-d loudspeaker output left ? c1 cf2 charge pump flyback capacitor, terminal 2 d1 agnd analog ground e1 cf1 charge pump flyback capacitor, terminal 1 a2 pvdd speaker power supply b2 pgnd speaker ground c2 cpvss charge pump negative supply for class-g d2 cpvdd charge pump positive supply for class-g e2 avdd analog power supply a3 rspk+ class-d loudspeaker output right + b3 rspk? class-d loudspeaker output right ? c3 scl 2-wire i 2 c control interface clock input d3 hpr class-g headphone output, right channel e3 hpl class-g headphone output, left channel a4 ep+ integrated switch output + b4 ep? integrated switch output ? c4 sda 2-wire i 2 c control interface data input/output d4 sd shutdown control, active low (optional limiter threshold voltage) e4 agnd analog ground a5 rcv+ baseband receiver (voice) input + b5 rcv? baseband receiver (voice) input ? c5 inb2 configurable input b2 (single-ended input b? or stereo input b, left channel) d5 inc2 configurable input c2 (single-ended input c? or stereo input c, left channel) e5 avdd analog power supply a6 ina1 configurable input a1 (single-ended input a+ or stereo input a, right channel) b6 ina2 configurable input a2 (single-ended input a? or stereo input a, left channel) c6 inb1 configurable input b1 (single-ended input b+ or stereo input b, right channel) d6 inc1 configurable input c1 (single-ended input c+ or stereo input c, right channel) e6 bias device bias pin
SSM2804 rev. 0 | page 9 of 36 typical performance characteristics 100 10 1 0.1 0.01 0.001 0.0001 10 thd + n (%) output power (w) 0.001 0.01 0.1 1 r l = 8 ? + 33h pvdd = 3.6v pvdd = 5v 09960-004 pvdd = 2.7v pvdd = 4.2v 100 10 1 0.1 0.01 0.001 0.0001 10 thd + n (%) output power (w) 0.001 0.01 0.1 1 r l = 4 ? + 15h 09960-005 pvdd = 2.7v pvdd = 4.2v pvdd = 3.6v pvdd = 5v figure 4. thd + n vs. output powe r into 8 , class-d amplifier, mono operation figure 7. thd + n vs. output powe r into 4 , class-d amplifier, mono operation 100 10 1 0.1 0.01 0.001 0.0001 10 thd + n (%) output power (w) 0.001 0.01 0.1 1 r l = 8 ? + 33h 09960-006 pvdd = 2.7v pvdd = 4.2v pvdd = 3.6v pvdd = 5v 100 10 1 0.1 0.01 0.001 0.0001 10 thd + n (%) output power (w) 0.001 0.01 0.1 1 r l = 4 ? + 15h 09960-007 pvdd = 2.7v pvdd = 4.2v pvdd = 3.6v pvdd = 5v figure 5. thd + n vs. output powe r into 8 , class-d amplifier, stereo operation figure 8. thd + n vs. output powe r into 4 , class-d amplifier, stereo operation 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 2.7v r l = 8 ? + 33h 62.5mw 300mw 125mw 09960-008 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 2.7v r l = 4 ? + 15h 62.5mw 125mw 500mw 250mw 09960-009 figure 6. thd + n vs. frequency, class-d amplifier, mono operation, r l = 8 , pvdd = 2.7 v figure 9. thd + n vs. frequency, class-d amplifier, mono operation, r l = 4 , pvdd = 2.7 v
SSM2804 rev. 0 | page 10 of 36 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 3.6v r l = 8 ? + 33h 09960-010 125mw 250mw 500mw 600mw figure 10. thd + n vs. frequency, cl ass-d amplifier, mono operation, r l = 8 , pvdd = 3.6 v 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 4.2v r l =8 ? + 33h 09960-012 125mw 900mw 500mw 250mw figure 11. thd + n vs. frequency, cl ass-d amplifier, mono operation, r l = 8 , pvdd = 4.2 v 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 5v r l = 8 ? + 33h 09960-014 500mw 1.2w 1w 250mw figure 12. thd + n vs. frequency, cl ass-d amplifier, mono operation, r l = 8 , pvdd = 5.0 v 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 3.6v r l =4 ? + 15h 09960-011 500mw 1.1w 125mw 250mw figure 13. thd + n vs. frequency, cl ass-d amplifier, mono operation, r l = 4 , pvdd = 3.6 v 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 4.2v r l =4 ? + 15h 09960-013 500mw 1.5w 1w 250mw figure 14. thd + n vs. frequency, cl ass-d amplifier, mono operation, r l = 4 , pvdd = 4.2 v 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 5v r l = 4 ? + 15h 250mw 500mw 1.5w 09960-015 2.2w figure 15. thd + n vs. frequency, cl ass-d amplifier, mono operation, r l = 4 , pvdd = 5.0 v
SSM2804 rev. 0 | page 11 of 36 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 4.0 4.5 5.0 output power (w) supply voltage (v) f = 1khz r l = 8 ? + 33h thd + n = 10% thd + n = 0.1% thd + n = 1% 09960-016 figure 16. output power vs. supply voltage, class-d amplifier, r l = 8 400 0 02 supply current (ma) output power (w) 50 100 150 200 250 300 350 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 . 0 pvdd = 2.7v pvdd = 3.6v pvdd = 4.2v pvdd = 5v r l = 8 ? + 33h 09960-018 figure 17. supply current vs. output power into 8 , class-d amplifier 100 90 80 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 efficiency (%) output power (w) r l = 8 ? + 33h 09960-020 pvdd = 2.7v pvdd = 3.6v pvdd = 4.2v pvdd = 5v figure 18. efficiency vs. output power into 8 , class-d amplifier 3.5 2.0 2.5 3.0 1.5 1.0 0.5 0 2.5 3.0 3.5 4.0 4.5 5.0 output power (w) supply voltage (v) f = 1khz r l = 4 ? + 15h thd + n = 10% thd + n = 0.1% thd + n = 1% 09960-017 figure 19. output power vs. supply voltage, class-d amplifier, r l = 4 800 0 03 supply current (ma) output power (w) 100 200 300 400 500 600 700 0.5 1.0 1.5 2.0 2.5 3.0 . 5 r l = 4 ? + 15h 09960-019 pvdd = 5v pvdd = 4.2v pvdd = 3.6v pvdd = 2.7v figure 20. supply current vs. output power into 4 , class-d amplifier 100 90 80 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 efficiency (%) output power (w) r l = 4 ? + 15h 09960-021 pvdd = 2.7v pvdd = 3.6v pvdd = 4.2v pvdd = 5v figure 21. efficiency vs. output power into 4 , class-d amplifier
SSM2804 rev. 0 | page 12 of 36 100 10 1 0.1 0.01 0.001 0.0001 10 thd + n (%) output power (w) 0.001 0.01 0.1 1 r l = 32 ? 09960-024 100 10 1 0.1 0.01 0.001 0.0001 10 thd + n (%) output power (w) 0.001 0.01 0.1 1 r l = 16 ? 09960-023 figure 22. thd + n vs. output power into 16 , headphone amplifier, stereo operation figure 25. thd + n vs. output power into 32 , headphone amplifier, stereo operation 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 2.7v r l = 16 ? 20mw 10mw 09960-025 100 10 1 0.1 0.01 0.001 10 100k thd + n (%) frequency (hz) 100 1k 10k pvdd = 2.7v r l = 32 ? 09960-026 10mw 5mw figure 23. thd + n vs. frequency, headphone amplifier, r l = 16 , pvdd = 2.7 v figure 26. thd + n vs. frequency, headphone amplifier, r l = 32 , pvdd = 2.7 v ?100 10 100k psrr (db) frequency (hz) 100 1k 10k ?90 ?120 ?110 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 09960-022 ?100 10 100k psrr (db) frequency (hz) 100 1k 10k ?90 ?120 ?110 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 09960-027 figure 27. power supply rejection ratio (psrr) vs. frequency, headphone amplifier figure 24. power supply rejection ratio (psrr) vs. frequency, class-d amplifier
SSM2804 rev. 0 | page 13 of 36 theory of operation the SSM2804 audio subsystem features a filterless modulation scheme that greatly reduces the external component count, con- serving board space and, thus, reducing system cost. the SSM2804 does not require an output filter but, instead, relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square wave output. m ost class-d amplifiers use some variation of pulse-width modulation (pwm), but the SSM2804 uses - modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. ? - modulators do not produce a sharp peak with many harmonics in the am frequency band, as pulse-width modulators often do. ? - modulation provides the benefits of reducing the amplitude of spectral components at high frequencies, that is, reducing emi emissions that might otherwise be radiated by speakers and long cable traces. ? the SSM2804 does not require external emi filtering for twisted speaker cable lengths shorter than 10 cm. if longer speaker cables are used, the SSM2804 has emission limiting circuitry that allows significantly longer speaker cable. ? due to the inherent spread-spectrum nature of - modu- lation, the need for modulator synchronization is eliminated for designs that incorporate multiple SSM2804 amplifiers. u sing the i 2 c control interface, the gain of the SSM2804 can be selected from a range of +12 db to ?63 db in 32 steps. other features accessed from the i 2 c interface include the following: ? independent left/right channel shutdown ? variable ultralow emi emission limiting circuitry ? automatic level control (alc) for high quality speaker protection ? stereo-to-mono mixing operation the SSM2804 also offers protection circuits for overcurrent and overtemperature protection. pop-and-click suppression voltage transients at the output of audio amplifiers can occur when shutdown is activated or deactivated. voltage transients as low as 10 mv can be heard as an audio pop in the speaker. clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. such transients may be generated when the amplifier system changes its operating mode. for example, the following may be sources of audible transients: system power-up and power-down, mute and unmute, input source change, and sample rate change. the SSM2804 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. output modulation description the SSM2804 uses three-level, - output modulation. each output can swing from gnd to v dd and vice versa. ideally, when no input signal is present, the output differential voltage is 0 v because there is no need to generate a pulse. in a real-world situation, noise sources are always present. due to the constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. a small amount of current flows into the inductive load when the differ- ential pulse is generated. most of the time, however, the output differential voltage is 0 v, due to the analog devices, inc., three-level, - output modu- lation. this feature ensures that the current flowing through the inductive load is small. when the user wants to send an input signal, an output pulse (out+ and out?) is generated to follow the input voltage. the differential pulse density (v out ) is increased by raising the input signal level. figure 28 depicts three-level, - output modulation with and without input stimulus. output > 0v +5v 0v out+ +5v 0v out? +5v 0v v out output < 0v +5v 0v out+ +5v 0v out? 0v ?5v v out output = 0v out+ +5v 0v +5v 0v out? +5v ?5v 0v v out 09960-104 figure 28. three-level, - output modulation with and without input stimulus
SSM2804 rev. 0 | page 14 of 36 hardware-based headphone limiter to provide fail-safe headphone level limiting independent of the register values sent to the amplifier over the i 2 c bus, the SSM2804 incorporates an optional hardware-based headphone limiter feature. the user controls the limiter level by supplying a voltage at the sd pin (see ). the hardware limiter is activated by setting the lim_mode bit to 0 in the additional control register (bit d3 of register 0x0e). after the desired limiter value is set, the user can lock the limiter setting by setting the limlock bit (bit d7 of register 0x0e). table 7 table 7. hardware limiter options limiter level power into 32 (mw) power into 16 (mw) sd pin voltage shutdown n/a n/a <0.87 v 0.40 v 2.5 5 0.87 v < v sd < 1.08 v 8 v 10 20 1.08 v < v sd < 1.29 v 1.13 v 20 40 v sd > 1.29 v note that after the hardware limiter lock bit is set, the locked levels cannot be reset until the SSM2804 is powered down, the sd pin is strobed low, or all eight bits of the software reset register (register 0x10) are set to 0. in addition to the hardware-based limiter, several other limiter levels can be selected using the i 2 c-based limiter function (set the hplim bits of register 0x0e; see tabl e 44 ). the effect of the limiter function on the headphone output is shown in figure 29 . 09960-028 ch1 500mv b w m20.0ms a ch1 110mv figure 29. limited headphone signal activating or deactivating the emission limiting circuitry to activate or deactivate the emission limiting circuitry, change the value of the edge bits in the additional control register (bits[d1:d0] of register 0x0e). four levels of emission control are available, allowing the user to determine the best trade-off between efficiency and emi reduction. in the default (fastest edge) mode, the user can pass fcc class-b emission testing with 10 cm twisted pair speaker wire for loudspeaker connection. if longer speaker wire is desired, change the edge setting to a slower edge rate mode. the trade-off is slightly lower efficiency and noise performance. the penalty for using the emission control circuitry is far less than the decreased performance observed when using a ferrite bead based emi filter for emission limiting purposes. automatic level control (alc) automatic level control (alc) is a function that automatically adjusts amplifier gain to generate the desired output amplitude with reference to a particular input stimulus. the primary use for the alc is to protect an audio power amplifier or speaker load from the damaging effects of clipping or current overloading. this is accomplished by limiting the output amplitude of the amplifier upon reaching a preset threshold voltage. another benefit of the alc is that it makes sound sources with a wide dynamic range more intelligible by boosting low level signals and limiting very high level signals. before activating the alc by setting the alcen bit (bit d7 of register 0x0b), the user has full control of the left and right channel pga gain. after the alc is activated (alcen = 1), the user has no control over the gain settings; the left channel pga gain is locked into the device and controls the gain for both the left and right channels. to change the gain, the user must reset the alcen bit to 0 and then load the new gain settings. figure 30 shows the response of the SSM2804 to a linearly increasing input signal. when the output reaches the current threshold value, the amplifier gain decreases by 0.5 db so that the output voltage remains under the threshold. as more atten- uation is added to the system, the threshold increases according to a profile determined by the compressor setting bits in the alc control 2 register (bits[d6:d5] of register 0x0b), causing a rounded knee as the output voltage approaches the output limiter level. the effect of this compression curve is shown in figure 30 . 5.6 5.2 4.8 4.4 4.0 3.6 3.2 2.8 2.4 1.6 1.2 2.0 0.8 0.4 0 0 20 40 60 80 100 120 140 160 180 200 time (ms) output voltage level (v) input gain = 6db gain = 12db gain = 18db gain = 24db 09960-034 figure 30. output response to linearly increasing input ramp signal when the input level is small and the output voltage is smaller than the alc threshold value, the gain of the amplifier stays at the preset gain setting. when the input exceeds the alc thresh- old value, the alc gradually reduces the gain from the preset gain setting down to 1 db.
SSM2804 rev. 0 | page 15 of 36 alc compression and limiter modes the alc implemented on the SSM2804 has two operation modes: compression mode and limiter mode. when the alc is triggered for medium-level input signals, the alc is in com- pression mode. in this mode, an increase of the output signal is one-third the increase of the input signal. for example, if the input signal increases by 3 db, the alc reduces the amplifier gain by 2 db and, thus, the output signal increases by only 1 db. as the input signal becomes very large, the alc transitions to limiter mode. in this mode, the output stays at a given threshold level, v th , even if the input signal grows larger. as an example of limiter mode operation, when a large input signal increases by 3 db, the alc reduces the amplifier gain by 3 db and, thus, the output increases by 0 db. when the amplifier gain is reduced to 1 db, the alc cannot reduce the gain further, and the output increases again. this is because the total range of the alc opera- tion has bottomed out due to extreme input voltage at high gain. to avoid potential speaker damage, the maximum input amplitude should not be large enough to exceed the maximum attenuation (to a level of 1 db) of the limiter mode. attack time, hold time, and release time when the amplifier input signal exceeds a preset threshold, the alc reduces amplifier gain rapidly until the output voltage settles to a target level. this target level is maintained for a certain period. if the input voltage does not exceed the threshold again, the alc increases the gain gradually. the attack time is the time taken to reduce the gain from maxi- mum to minimum. the hold time is the time that the reduced gain is maintained. the release time is the time taken to increase the gain from minimum to maximum. these times are shown in table 8 . the attack time and the release time can be set using the alc 1 control register (address 0x0a). table 8. alc attack, hold, and release times time 1 duration attack time 32 s to 4 ms (per 0.5 db step) hold time 90 ms to 120 ms release time 4 ms to 512 ms (per 0.5 db step) 1 the attack time and release t ime can be adjusted using the i 2 c interface. the hold time cannot be adjusted. soft-knee compression often performed using sophisticated dsp algorithms, soft-knee compression provides maximum sound quality with effective speaker protection. instead of using a fixed compression setting prior to limiting, the SSM2804 allows for a much more subtle transition into limiting mode, preserving the original sound quality of the source audio. figure 31 to figure 33 show the various soft-knee compression settings that can be selected using the comp bit settings (bits[d6:d5] of register 0x0b). 0 0.5 1.0 1.5 2.0 2.5 0 0.05 0.10 0.15 0.20 0.30 0.35 0.40 0.45 0.25 0.50 input voltage (v) output voltage (v) 00 (compression mode 1) 01 (compression mode 2) 10 (compression mode 3) 11 (limiter mode) 2.7v 0.78 = 2.106v 09960-107 figure 31. adjustable compression settings, pvdd = 2.7 v, alc threshold level = 78% 0 0.5 1.5 2.0 2.5 1.0 3.0 3.5 0 0.1 0.2 0.3 0.4 0.6 0.7 0.8 0.9 0.5 1.0 input voltage (v) output voltage (v) 00 (compression mode 1) 01 (compression mode 2) 10 (compression mode 3) 11 (limiter mode) 3.6v 0.78 = 2.808v 0 9960-118 figure 32. adjustable compression settings, pvdd = 3.6 v, alc threshold level = 78% 0 0.5 1.5 2.0 2.5 1.0 3.0 4.0 3.5 4.5 0 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 1.0 2.0 input voltage (v) output voltage (v) 00 (compression mode 1) 01 (compression mode 2) 10 (compression mode 3) 11 (limiter mode) 5.0v 0.78 = 3.9v 0 9960-119 figure 33. adjustable compression settings, pvdd = 5.0 v, alc threshold level = 78%
SSM2804 rev. 0 | page 16 of 36 soft transition (32s to 256s) norm a l transition 0.5db 0.5db 09960-108 alc soft transition the alc operation of the SSM2804 incorporates techniques to reduce the audible artifacts associated with gain change transi- tions. first, the gain is changed in small increments of 0.5 db. in addition to this small step size, the rate of gain change is reduced, proportional to the attack time setting. this feature drastically reduces and virtually eliminates the presence of zipper noise and other artifacts associated with gain transitions during alc operation. figure 34 shows the soft transition operation. figure 34. soft transition
SSM2804 rev. 0 | page 17 of 36 typical application circuits boost = 0db to +20db pga = ?12db to +18db +12db to ?63db 31 steps class-d class-g 0db to ?75db 32 steps ina2 rcv? rcv+ rcv in? lspk in? (diff in1?) lspk in+ (diff in1+) mp3 inl (diff in2?) mp3 inr (diff in2+) fm inl (diff in3?) fm inr (diff in3+) rcv in+ ep? earpiece ep+ lspk+ hpl headphone output left headphone output right class-d output left class-d output right lspk? rspk+ rspk? ina1 boost = 0db to +20db pga = ?12db to +18db inb2 inb1 mix/mux boost = 0db to +20db pga = ?12db to +18db inc2 inc1 cf1 cf2 cpvdd sd hpr bias i 2 c class-g supply bias agnd pgnd scl sda 1f to 2.2f 1f to 2.2f 1f cpvss ?2.2v to +1.2v i 2 c data i 2 c clock cpvss pvdd avdd SSM2804 09960-031 10f 0.1f vbatt 2.7v to 5.5v cpvdd 1.2v to 2.2v 10f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f avdd 2.5v to 3.6v shutdown figure 35. application circuit with external components
SSM2804 rev. 0 | page 18 of 36 mix/mux bypass class-d class-g 1.2v < cpvdd < +2.2v/?2.2v < cpvss < ?1.2v (internally generated) 2.7v < pvdd < 5v 2.5v < avdd < 3.6v 09960-032 figure 36. powe r supply domains
SSM2804 rev. 0 | page 19 of 36 i 2 c software control interface the i 2 c interface provides access to the user-selectable control registers and operates with a 2-wire interface. each control register consists of 16 bits, msb first. bits[b15:b9] are the register map address, and bits[b8:b0] are the register data for the associated register map. sda generates the serial control data-word, and scl clocks the serial data. the i 2 c bus address (bits[a7:a1]) is 0x3b (01110110 for write and 01110111 for read). bit a0 is the designated read/write bit. p 98 1to 7 98 1to 7 98 1to 7 s sda scl start addr r/w ack ack subaddress ack stop data 09960-029 figure 37. 2-wire i 2 c generalized clocking diagram write sequence read sequence sa 1 a7 a0 a(s) a(s) s b15 b9 0 01 0p 0 ... a1 a7 a0 a(s) ... b0 b8 b7 a(m) a(m) ... b0 b7 p ... ... ... device address device address register address sa 1 a7 a0 a(s) a(s) a(s) b15 b9 b8 0 ... ... device address register address register data (slave drive) register data s/p = start/stop bit. a0 = i 2 c r/w bit. a(s) = acknowledge by slave. a (m) = acknowledge by master. a (m) = acknowledge by master (inversion). 09960-030 figure 38. i 2 c write and read sequences
SSM2804 rev. 0 | page 20 of 36 register map the 7-bit i 2 c address of the SSM2804 is 0x3b (0111011). table 9. register map address name d7 d6 d5 d4 d3 d2 d1 d0 default 0x00 input mode 0 zcd gain mod[2:0] inmod[2:0] 0x00 0x01 ina volume 0 0 0 inavol[4:0] 0x00 0x02 inb volume 0 0 0 inbvol[4:0] 0x00 0x03 inc volume 0 0 0 incvol[4:0] 0x00 0x04 class-d left volume 0 0 0 lcdvol[4:0] 0x00 0x05 class-d right volume 0 0 0 rcdvol[4:0] 0x00 0x06 lhp volume 0 0 0 lhpvol[4:0] 0x00 0x07 rhp volume 0 0 0 rhpvol[4:0] 0x00 0x08 hp input mixer poptime[1:0] rhpmod[2:0] lhpmod[2:0] 0x00 0x09 class-d input mixer cdsm[1:0] rcdmod[2:0] lcdmod[2:0] 0x00 0x0a alc control 1 0 0 rectime[2:0] attime[2:0] 0x2b 0x0b alc control 2 alcen comp[1:0] alclv_fix alclv[3:0] 0x4b 0x0c alc control 3 0 lcdboost rcdboost so ftstart softclipen ngen ngate[1:0] 0x00 0x0d power-down control passpdb incpdb inbpdb inapdb rcdpdb lcdpdb hppdb pwdb 0x00 0x0e additional control limlock hplim[2:0] lim_mod to edge[1:0] 0x00 0x0f chip status 1 0 0 0 0 occd ochp ow ot 0x00 0x10 software reset 2 softreset 0x00 1 this byte is read-only. 2 this byte is write-only.
SSM2804 rev. 0 | page 21 of 36 register map details input channel mode control, address 0x00 table 10. input channel mode control register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 zcd gainmod[2:0] inmod[2:0] table 11. input channel mode control register bit descriptions bit name description settings zcd zero cross-detector enable 0 = disable (default) 1 = enable gainmod[2:0] input amplifier gain mode xx0 = input a pga mode xx1 = input a boost mode x0x = input b pga mode x1x = input b boost mode 0xx = input c pga mode 1xx = input c boost mode inmod[2:0] input mode control xx0 = input a stereo mode (ina1, ina2 > inal, inar) xx1 = input a differential mode (ina1, ina2 > ina+, ina?) x0x = input b stereo mode (inb1, inb2 > inbl, inbr) x1x = input b differential mode (inb1, inb2 > inb+, inb?) 0xx = input c stereo mode (inc1, inc2 > incl, incr) 1xx = input c differential mode (inc1, inc2 > inc+, inc?) see table 12 for complete information about the naming table table 12. input mode naming table inmod[2:0] ina1 pin ina2 pin in b1 pin inb2 pin inc1 pin inc2 pin 000 inal inar inbl inbr incl incr 001 inal inar inbl inbr inc+ inc? 010 inal inar inb+ inb? incl incr 011 inal inar inb+ inb? inc+ inc? 100 ina+ ina? inbl inbr incl incr 101 ina+ ina? inbl inbr inc+ inc? 110 ina+ ina? inb+ inb? incl incr 111 ina+ ina? inb+ inb? inc+ inc?
SSM2804 rev. 0 | page 22 of 36 channel a line input volume, address 0x01 table 13. channel a line input volume register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 inavol[4:0] table 14. channel a line input volume register bit descriptions bit name description settings inavol[4:0] analog channel a input volume control see table 15 table 15. descriptions of channel a volume register bits inavol[4:0] pga mode (db) boost mode (db) 00000 mute mute 00001 ?12 0 00010 ?11 0 00011 ?10 0 00100 ?9 0 00101 ?8 0 00110 ?7 0 00111 ?6 0 01000 ?5 0 01001 ?4 0 01010 ?3 0 01011 ?2 0 01100 ?1 0 01101 0 0 01110 1 9 01111 2 9 10000 3 9 10001 4 9 10010 5 9 10011 6 9 10100 7 20 10101 8 20 10110 9 20 10111 10 20 11000 11 20 11001 12 20 11010 13 20 11011 14 20 11100 15 20 11101 16 20 11110 17 20 11111 18 20
SSM2804 rev. 0 | page 23 of 36 channel b line input volume, address 0x02 table 16. channel b line input volume register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 inbvol[4:0] table 17. channel b line input volume register bit descriptions bit name description settings inbvol[4:0] analog channel b input volume control see table 18 table 18. descriptions of channel b input volume register bits inbvol[4:0] pga mode (db) boost mode (db) 00000 mute mute 00001 ?12 0 00010 ?11 0 00011 ?10 0 00100 ?9 0 00101 ?8 0 00110 ?7 0 00111 ?6 0 01000 ?5 0 01001 ?4 0 01010 ?3 0 01011 ?2 0 01100 ?1 0 01101 0 0 01110 1 9 01111 2 9 10000 3 9 10001 4 9 10010 5 9 10011 6 9 10100 7 20 10101 8 20 10110 9 20 10111 10 20 11000 11 20 11001 12 20 11010 13 20 11011 14 20 11100 15 20 11101 16 20 11110 17 20 11111 18 20
SSM2804 rev. 0 | page 24 of 36 channel c line input volume, address 0x03 table 19. channel c line input volume register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 incvol[4:0] table 20. channel c line input volume register bit descriptions bit name description settings incvol[4:0] analog channel c input volume control see table 21 table 21. descriptions of channel c input volume register bits incvol[4:0] pga mode (db) boost mode (db) 00000 mute mute 00001 ?12 0 00010 ?11 0 00011 ?10 0 00100 ?9 0 00101 ?8 0 00110 ?7 0 00111 ?6 0 01000 ?5 0 01001 ?4 0 01010 ?3 0 01011 ?2 0 01100 ?1 0 01101 0 0 01110 1 9 01111 2 9 10000 3 9 10001 4 9 10010 5 9 10011 6 9 10100 7 20 10101 8 20 10110 9 20 10111 10 20 11000 11 20 11001 12 20 11010 13 20 11011 14 20 11100 15 20 11101 16 20 11110 17 20 11111 18 20
SSM2804 rev. 0 | page 25 of 36 class-d left loudspeaker output volume, address 0x04 table 22. class-d left loudspeaker output volume register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 lcdvol[4:0] table 23. class-d left loudspeaker outp ut volume register bit descriptions bit name description settings lcdvol[4:0] left channel class-d vo lume control 00000 = mute (default) 00001 = ?75 db 00010 = ?71 db 00011 = ?67 db 00100 = ?63 db 00101 = ?59 db 00110 = ?55 db 00111 = ?51 db 01000 = ?47 db 01001 = ?44 db 01010 = ?41 db 01011 = ?38 db 01100 = ?35 db 01101 = ?32 db 01110 = ?29 db 01111 = ?26 db 10000 = ?23 db 10001 = ?21 db 10010 = ?19 db 10011 = ?17 db 10100 = ?15 db 10101 = ?13 db 10110 = ?11 db 10111 = ?9 db 11000 = ?7 db 11001 = ?6 db 11010 = ?5 db 11011 = ?4 db 11100 = ?3 db 11101 = ?2 db 11110 = ?1 db 11111 = 0 db
SSM2804 rev. 0 | page 26 of 36 class-d right loudspeaker output volume, address 0x05 table 24. class-d right loudspeaker output volume register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 rcdvol[4:0] table 25. class-d right loudspeaker outp ut volume register bit descriptions bit name description settings rcdvol[4:0] right channel class-d vo lume control 00000 = mute (default) 00001 = ?75 db 00010 = ?71 db 00011 = ?67 db 00100 = ?63 db 00101 = ?59 db 00110 = ?55 db 00111 = ?51 db 01000 = ?47 db 01001 = ?44 db 01010 = ?41 db 01011 = ?38 db 01100 = ?35 db 01101 = ?32 db 01110 = ?29 db 01111 = ?26 db 10000 = ?23 db 10001 = ?21 db 10010 = ?19 db 10011 = ?17 db 10100 = ?15 db 10101 = ?13 db 10110 = ?11 db 10111 = ?9 db 11000 = ?7 db 11001 = ?6 db 11010 = ?5 db 11011 = ?4 db 11100 = ?3 db 11101 = ?2 db 11110 = ?1 db 11111 = 0 db
SSM2804 rev. 0 | page 27 of 36 left headphone output volume, address 0x06 table 26. left headphone outp ut volume register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 lhpvol[4:0] table 27. left headphone output volume register bit descriptions bit name description settings lhpvol[4:0] left headphone output vo lume control 00000 = mute (default) 00001 = ?75 db 00010 = ?71 db 00011 = ?67 db 00100 = ?63 db 00101 = ?59 db 00110 = ?55 db 00111 = ?51 db 01000 = ?47 db 01001 = ?44 db 01010 = ?41 db 01011 = ?38 db 01100 = ?35 db 01101 = ?32 db 01110 = ?29 db 01111 = ?26 db 10000 = ?23 db 10001 = ?21 db 10010 = ?19 db 10011 = ?17 db 10100 = ?15 db 10101 = ?13 db 10110 = ?11 db 10111 = ?9 db 11000 = ?7 db 11001 = ?6 db 11010 = ?5 db 11011 = ?4 db 11100 = ?3 db 11101 = ?2 db 11110 = ?1 db 11111 = 0 db
SSM2804 rev. 0 | page 28 of 36 right headphone output volume, address 0x07 table 28. right headphone output volume register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 rhpvol[4:0] table 29. right headphone output volume register bit descriptions bit name description settings rhpvol[4:0] right headphone output vo lume control 00000 = mute (default) 00001 = ?75 db 00010 = ?71 db 00011 = ?67 db 00100 = ?63 db 00101 = ?59 db 00110 = ?55 db 00111 = ?51 db 01000 = ?47 db 01001 = ?44 db 01010 = ?41 db 01011 = ?38 db 01100 = ?35 db 01101 = ?32 db 01110 = ?29 db 01111 = ?26 db 10000 = ?23 db 10001 = ?21 db 10010 = ?19 db 10011 = ?17 db 10100 = ?15 db 10101 = ?13 db 10110 = ?11 db 10111 = ?9 db 11000 = ?7 db 11001 = ?6 db 11010 = ?5 db 11011 = ?4 db 11100 = ?3 db 11101 = ?2 db 11110 = ?1 db 11111 = 0 db
SSM2804 rev. 0 | page 29 of 36 headphone input mixer control, address 0x08 table 30. headphone input mixer control register bit map d7 d6 d5 d4 d3 d2 d1 d0 poptime[1:0] rhpmod[2:0] lhpmod[2:0] table 31. headphone input mixer control register bit descriptions bit name description settings poptime[1:0] headphone turn-on time constant setting 00 = 10 ms (default) 01 = 20 ms 10 = 40 ms 11 = 80 ms (smallest pop-and-click) rhpmod[2:0] right headphone input mixer xx0 = analog input a disabled (default) xx1 = analog input a enabled x0x = analog input b disabled (default) x1x = analog input b enabled 0xx = analog input c disabled (default) 1xx = analog input c enabled lhpmod[2:0] left headphone input mixer xx0 = analog input a disabled (default) xx1 = analog input a enabled x0x = analog input b disabled (default) x1x = analog input b enabled 0xx = analog input c disabled (default) 1xx = analog input c enabled class-d input mixer control, address 0x09 table 32. class-d input mixer control register bit map d7 d6 d5 d4 d3 d2 d1 d0 cdsm[1:0] rcdmod[2:0] lcdmod[2:0] table 33. class-d input mixer control register bit descriptions bit name description settings cdsm[1:0] class-d stereo/mono mode control x0 = left channel disabled (default) x1 = left channel enabled (left and right) 0x = right channel disabled (default) 1x = right channel enabled (left and right) rcdmod[2:0] right class-d input mixer xx0 = analog input a disabled (default) xx1 = analog input a enabled x0x = analog input b disabled (default) x1x = analog input b enabled 0xx = analog input c disabled (default) 1xx = analog input c enabled lcdmod[2:0] left class-d input mixer xx0 = analog input a disabled (default) xx1 = analog input a enabled x0x = analog input b disabled (default) x1x = analog input b enabled 0xx = analog input c disabled (default) 1xx = analog input c enabled
SSM2804 rev. 0 | page 30 of 36 alc control 1, address 0x0a table 34. alc control 1 register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 0 rectime[2:0] attime[2:0] table 35. alc control 1 register bit descriptions bit name description settings rectime[2:0] alc release rate 000 = 4 ms per 0.5 db step (6 db/48 ms) 001 = 8 ms 010 = 16 ms 011 = 32 ms 100 = 64 ms 101 = 128 ms (default) 110 = 256 ms 111 = 512 ms attime[2:0] alc attack rate 000 = 32 s per 0.5 db step (6 db/384 s) 001 = 64 s 010 = 128 s 011 = 256 s (default) 100 = 512 s 101 = 1 ms 110 = 2 ms 111 = 4 ms
SSM2804 rev. 0 | page 31 of 36 alc control 2, address 0x0b table 36. alc control 2 register bit map d7 d6 d5 d4 d3 d2 d1 d0 alcen comp[1:0] alclv_fix alclv[3:0] table 37. alc control 2 register bit descriptions bit name description settings alcen alc enable 0 = alc disabled (default) 1 = alc enabled comp[1:0] compressor setting (see the soft-knee compression section for more information) 00 = compression mode 1 (1:4 to 1:) 01 = compression mode 2 (1:1.7 to 1:4 to 1:) 10 = compression mode 3 (1:1.3 to 1:2.5 to 1:) 11 = limiter mode (1:) alclv_fix alc threshold mode setting 0 = supply tracking (threshold is a constant fraction of supply voltage) 1 = fixed power (threshold is a fixed voltage) alclv[3:0] alc threshold level setting see table 38 table 38. alc threshold levels supply tracking threshold (% of pvdd) fixed power threshold (v) alclv[3:0] value (alclv_fix = 0) (alclv_fix = 1) 0000 65 2.74 0001 67 2.89 0010 69 3.04 0011 72 3.19 0100 75 3.34 0101 78 3.50 0110 81 3.65 0111 85 3.80 1000 88 3.95 1001 93 4.10 1010 97 4.25 1011 102 4.40 1100 108 4.56 1101 114 4.71 1110 122 4.86 1111 130 5.01
SSM2804 rev. 0 | page 32 of 36 alc control 3, address 0x0c table 39. alc control 3 register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 lcdboost rcdboost softstart softclipen ngen ngate[1:0] table 40. alc control 3 register bit descriptions bit name description settings lcdboost left channel class-d gain boost 0 = 0 db (default) 1 = +6 db boost rcdboost right channel class-d gain boost 0 = 0 db (default) 1 = +6 db boost softstart soft start enable 0 = soft start disabled (default) 1 = soft start enabled softclipen soft clip enable 0 = soft clip disabled (default) 1 = soft clip enabled ngen noise gate enable 0 = no ise gate disabled (default) 1 = noise gate enabled ngate[1:0] noise gate level 00 = 2 mv (default) 01 = 4 mv 10 = 8 mv 11 = 16 mv power-down control, address 0x0d table 41. power-down control register bit map d7 d6 d5 d4 d3 d2 d1 d0 passpdb incpdb inbpdb inapdb rcdpdb lcdpdb hppdb pwdb table 42. power-down control register bit descriptions bit name description settings passpdb passive switch power-down 0 = power down (default) 1 = power up incpdb input channel c power-down 0 = power down (default) 1 = power up inbpdb input channel b power-down 0 = power down (default) 1 = power up inapdb input channel a power-down 0 = power down (default) 1 = power up rcdpdb class-d right channel power-down 0 = power down (default) 1 = power up lcdpdb class-d left channel power-down 0 = power down (default) 1 = power up hppdb headphone power-down 0 = power down (default) 1 = power up pwdb system power-down 0 = power down (default) 1 = power up
SSM2804 rev. 0 | page 33 of 36 ep? ep+ lspk+ hpl lspk? rspk+ rspk? hpr 09960-035 ina2 inapdb inbpdb incpdb pwdb cf1 hppdb rcdpdb lcdpdb passpdb cf2 rcv? rcv+ ina1 inb2 inb1 mix/mux inc2 inc1 sd bias i 2 c class-g supply agnd pvdd a v dd SSM2804 cf1 cf2 cpvdd pgnd scl sda cpvss figure 39. power management control register blocks
SSM2804 rev. 0 | page 34 of 36 additional control, address 0x0e table 43. additional control register bit map d7 d6 d5 d4 d3 d2 d1 d0 limlock hplim[2:0] lim_mode to edge[1:0] table 44. additional control register bit descriptions bit name description settings limlock headphone limiter lock bi t. after the limiter is locked, the locked levels cannot be reset until the SSM2804 is powered down, the sd pin is strobed low, or all eight bits of the software reset register (register 0x10) are set to 0. 0 = disable (default) 1 = enable hplim[2:0] headphone limiter level adjust. 000 = off (default) 001 = 1.13 v 010 = 0.98 v 011 = 0.80 v 100 = 0.57 v 101 = 0.40 v 110 = 0.28 v 111 = 0.22 v lim_mode headphone limiter mode selection. 0 = hardware mode (external resistor limiter via sd pin; default) 1 = software mode (i 2 c adjustable limiter) to timeout control. 0 = 30 ms (default) 1 = 60 ms edge[1:0] class-d output stage edge co ntrol. 00 = normal mode (default) 01 = slow edge 10 = slower edge (pvdd > 3.0 v recommended) 11 = slowest edge (pvdd > 4.0 v recommended)
SSM2804 rev. 0 | page 35 of 36 chip status register, address 0x0f this register is read-only. table 45. chip status register bit map d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 occd ochp ow ot table 46. chip status re gister bit descriptions bit name description settings occd overcurrent for class-d 0 = normal 1 = overcurrent ochp overcurrent for headphone 0 = normal 1 = overcurrent ow overtemperature warning 0 = normal 1 = overtemperature warning ot overtemperature error (thermal shutdown) 0 = normal 1 = overtemperature shutdown software reset register, address 0x10 this register is write-only. table 47. software reset register bit map d7 d6 d5 d4 d3 d2 d1 d0 softreset table 48. software reset register bit descriptions bit name description settings softreset software reset 00000000 = software reset
SSM2804 rev. 0 | page 36 of 36 outline dimensions a b c d e 0.660 0.600 0.540 3.000 2.960 2.920 12 3 456 bottom view (ball side up) top view (ball side down) side view 0.270 0.240 0.210 0.390 0.360 0.330 0.360 0.320 0.280 2.00 ref 2.50 ref ball a1 identifier coplanarity 0.05 seating plane 2.500 2.460 2.420 0.50 ball pitch 06-29-2010-b figure 40. 30-ball wafer level chip scale package [wlcsp] (cb-30-4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option SSM2804cbz-rl ?40c to +85c 30-ball wafer level chip scale package [wlcsp] cb-30-4 SSM2804cbz-r7 ?40c to +85c 30-ball wafer level chip scale package [wlcsp] cb-30-4 eval-SSM2804z evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09960-0-7/11(0)

▲Up To Search▲

Price & Availability of SSM2804

	To Download SSM2804 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .